Computer Performance Evaluation and Benchmarking: SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, ProceedingsDavid Kaeli, Kai Sachs This book constitutes the proceedings of the SPEC Benchmark Workshop 2009 held in Austin, Texas, USA on January 25th, 2009. The 9 papers presented were carefully selected and reviewed for inclusion in the book. The result is a collection of high-quality papers discussing current issues in the area of benchmarking research and technology. The topics covered are: benchmark suites, CPU benchmarking, power/thermal benchmarking, and modeling and sampling techniques. |
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Common terms and phrases
access duration access pattern allocation analysis applications average benchmarks branch misprediction branch predictor buffer cache line cache line set cache misses CISC components Computer configurations core counts the number cycles data cache data cache miss data stalls Derby design space DTLB miss entries event counts execution experiments floating-point hardware performance counters indirect branches instruction cache Itanium ITLB L1 data cache L2 cache L2 DTLB latency load M/G/1 queue mean number measured memory architecture metric microarchitecture MISPRED misprediction rate miss rate miss ratios models Montecito mpegaudio multi-core neural networks number of customers optimization parameters Platform Intel Server pointer power consumption POWER5+ prediction prefetcher processor programs RISC Scimark scimark.fft.large scimark.fft.small scimark.lu.large scimark.lu.small scimark.monte_carlo service time distribution SimPoint simulation points SPEC CPU SPECfp SPECInt SPECjAppServer2004 SPECrate Table thermal behavior uintptr_t UltraSPARC T2 uops uops/inst wavelet coefficients Woodcrest workload xml.validation