Computer Architecture: A computer zoo, ch. 9-16 |
Contents
Harvard Mark I | 524 |
Machine designation | 527 |
Architects dates family tree | 533 |
11 other sections not shown
Common terms and phrases
accumulator addend address field address register addressing modes architecture Arithmetic Shift augend basic cycle binary bits Bull Gamma 60 Burroughs B5500 byte Cambridge EDSAC coefficient comparand Conditional Branch control store control word Count Cray DEC PDP11 DEC PDP8 decimal Decrement descriptor dest digits Divide ENDCASE C2 ENDIF execute exponent Ferranti Mark fixed-point arithmetic floating point floating-point function halfword Harvard Mark high-order iadr IBM Stretch IBM System/360 Immediate implementation Increment index registers indicators Input/Output instruction address Instruction allocation instruction fetch integer interrupt Legend Load and Store logical low-order machine magni magnr mask mnemonics modifier Motorola Multiply normal Opcode operand Operand Specification operation code overflow Princeton IAS processor radix radixcompr reg fld representation result scalar sequencing Shift Arithmetic specified stack pointer status STC ZEBRA Stop subroutine sum augend+addend switch tape Test Univac vector zero Zuse Z4