Computer Arithmetic, Volume 2Earl E. Swartzlander IEEE Computer Society Press, 1990 - Computer arithmetic |
Contents
Error Tolerant Arithmetic | 15 |
Generalized Parity Checking | 30 |
Error Detection and Correction for Addition and Subtraction through Use of Higher | 48 |
Copyright | |
19 other sections not shown
Other editions - View all
Common terms and phrases
5th Symposium addition arithmetic operations array binary numbers block carry lookahead carry lookahead adder carry-save carry-save adder chip Computer Arithmetic conventional conversion cycle digit on-line division divisor Electronics error correction error detection exponent fixed-slash number floating point floating-point number floating-slash FLPOL fraction full adder function gate Hamming codes hardware IEEE Trans IEEE Transactions implementation input integer iteration layout Lemma logic mantissa modulo multiplier n-bit normalized number system on-line algorithms on-line arithmetic on-line delay one's complement operands optimal output overflow parallel parity check partial product partial remainder performed pipeline position precision Proc Proceedings processor quotient digits radix range redundant binary residue Residue Number System result rounding scheme shift shown in Fig signed-digit representation significand single error Solid-State Circuits square root subtraction Symposium on Computer systolic array Table tion Transactions on Computers two's complement values VLSI zero