Hardware Mechanisms to Support Concurrent Threads on RISC and Superscalar Multiprocessors |
Contents
Branches | 4 |
Memory Latency and Synchronization | 10 |
Hardware Description | 18 |
Copyright | |
2 other sections not shown
Common terms and phrases
algorithm Annual Symp Appendix branch instruction CALIFORNIA SANTA CRUZ calli M[CP cessor cmppt column comparison routines compiler Computer Architecture concurrent threads context switch CPIsimulated CRUZ The University cycles cycles/transfer dataflow coprocessor Dataflow Languages Daxpy iteration Decode Eqntott FIFO Figure floating-point Fortran hardware hide memory latency hybrid architecture i+4 th instruction IEEE indirect branch instruction i+1 th latency and synchronization Library UNIVERSITY Linpack matrix multiplication mechanism microprocessor multiprocessor system object-based Object-based Languages object-oriented object-oriented programming operand optimum utilization pfadd pfld pfld pfmul pfadd pfadd pipelined architecture Pipelined Processors predict prefetch unit private memory procedural interfaces procedure-level granularity remote procedure call RISC and Superscalar sequential instruction shared-memory simulations sort algorithm speedup store R1 M[CP Superpipelined superscalar architecture Superscalar Multiprocessors synchronization points synchronization variable Table th instruction Execute th instruction i+3 th instruction instruction trace scheduling UNIVERSITY OF CALIFORNIA vector length vector routine VLIW