High-speed Memory Systems |
Contents
Chapter | 11 |
BASICS OF BUFFERED CACHE | 17 |
DESIGN OF CACHE MEMORY | 23 |
Copyright | |
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Common terms and phrases
address array address translation allocated associative assumed average backing store block size buffered memory system bus requests bus traffic cache memory central memory check bits computed cost D₁ data array data cache delay devices double word effective cycle failure rate fast buffer fault ratio Figure flagged swap Fraction of Reads frequency index array instruction Latch logical address main memory Main module main storage mapping memory cycle memory hierarchy memory management Memory Management Unit memory references memory requests miss ratio Multiprocessor multiprogrammed organized P₁ page fault page table paging disk parameters parity parity bits performance physical address space processor registers scheme SEARCH INTERRUPT segment speed stack swap algorithm switched syndrome bits table entry technique Teff TFRC TFWC TSRC TSRH TSWC virtual address virtual memory system write operations write through algorithm WT Algorithm