1985 IEEE International Solid-State Circuits Conference: Digest of Technical Papers |
Common terms and phrases
A/D converter achieved Acknowledgments The authors analog analog circuits antifuse architecture bipolar bit line bitline bytes capacitance cascode channel chip circuit circuitry clock CMOS column conventional current mirror cycle decoder delay density detector device differential DIGEST OF TECHNICAL DRAM emitter EPROM error fabricated filter frequency full adder functions GaAs gate array high speed high-speed IEEE implemented input integrated interconnection interface ISSCC ISSCC DIGEST Japan latch layer layout load logic macrocell array memory cell metal mode MOSFET multiplier NMOS on-chip opamp operation performance poly polycide polysilicon power dissipation processor pulse reduce resistor sense amplifier SESSION shown in Figure signal processing silicon soft error SRAM substrate supply voltage switched capacitor Table TECHNICAL PAPERS techniques temperature THPM tion transistor VLSI waveforms word line wordline