Microprogrammable Computer Architectures |
Contents
Architectural Facilities | 17 |
X | 21 |
Microinstructions and Control | 32 |
Copyright | |
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16 bits Adder addition arithmetic AUXO bits in length branches Burroughs B1700 buses byte capabilities control fields control memory control register control store data width Decode emulation encoding executed external store F register F store facilities fetched file registers floating point Format fullword functional units GATE halfword hardware horizontal incremented Index ALU input input/output instruction register Interdata 8/32 interrupt KALC logic machine language macro main memory main store mask memory access memory address micro level architecture Microdata microinstruction microprogram mode module Monobus nano store Nanodata nanoprimitives nanoprogram nanoword OP code operand operations options output Port processor purpose registers read-only memory read-write Register Set residual control scratchpad selected shift shifter shown in Figure specified storage store registers target instruction target machine TEST tion transfer user level 8/32 utilized vector vertical word Z-Machine