PA-RISC 2.0 ArchitectureHewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA- RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor. For system designers and analysts, system software programmers, application developers, and technical managers. |
Contents
Figure | 2-1 |
Processing Resources | 2-2 |
Instruction Set Overview | 2-6 |
Copyright | |
21 other sections not shown
Common terms and phrases
absolute accesses absolute address access rights address space address translation assembly language assembly language completer Assist emulation trap Assist exception trap base register modification bits bits bits branch instruction byte cache control hint cache line cond_satisfied control registers coprocessor current instruction current privilege level data cache Data memory Description doubleword effective address encoded exception registers executed ext4 flush following instruction GR[t halfword hardware IIA Queue implementation index register instruction address instruction causing instruction is nullified Interruption Instruction invalid language completer mnemonics leftmost bit load and store long displacement Major Opcode move-in Offset Computation offset GR[b opd1 opd2 operand PA-RISC page fault Page Table physical address privilege level processor protection ID PSW W-bit PSW[N purge Q-bit reference trap result satisfy the specified semaphore short displacement space ID space identifier space register specified condition Status Register switch cmplt TLB entry undefined operation unsigned virtual address word zero