PCI Hardware and Software: Architecture and Design |
Common terms and phrases
32 data 64 data bit add-in card ADDRESS PHASE Base Address Base Address Register bit PCI bus BURST access cycle bus cycle Bus Number C/BE cache controller cache line CLK signal line complete configuration access cycle configuration address space Configuration Manager connector data bit PCI DATA PHASE deasserted decode defined device drivers DEVSEL DUAL ADDRESS expansion ROM Fast Back-to-Back Figure function hardware HDRAM HOST bus HOST CPU HOST/PCI BRIDGE implemented interrupt acknowledge cycle Interrupt Pin IRDY LEGACY bus line is asserted Lock master memory address memory write microprocessor PAR64 signal lines parity error PCI bus master PCI configuration space PCI device PCI resource PCI/PCI bridge PDRAM platform Prefetchable prefetchable memory protocol pull-up resistors read access cycle Retry termination SDONE signal line SERR shadow RAM signal line period special cycle Status Register System BIOS system resources Target Abort termination transaction TRDY valid write access cycle