Rapid Prototyping of Digital Systems: SOPC EditionNew to this edition is an introduction to embedded operating systems for SOPC designs. Featuring four accelerated tutorials on the Quartus II and Nios II design environments, this edition progresses from introductory programmable logic to full-scale SOPC design integrating hardware implementation, software development, operating system support, state-of-the-art I/O, and IP cores. This edition features Altera's new 7.1 Quartus II CAD and Nios II SOPC tools and includes projects for Altera's DE1, DE2, UP3, UP2, and UP1 FPGA development boards. |
Contents
Testing Your Design on an FPGA Board | 18 |
Downloading Your Design to the UP3 Board | 25 |
Compiling the VHDL Design | 32 |
Laboratory | 42 |
Programmable Logic | 55 |
Sequential Design and Hierarchy | 75 |
FPGAcore Library Functions | 87 |
Using Verilog for Synthesis of Digital Hardware ________________ | 130 |
Legacy Digital IO Interfacing Standards ______________________ | 232 |
FPGA Robotics Projects ____________________________________ | 242 |
Synthesis of the MIPS Processor Core | 283 |
Introducing SystemonaProgrammableChip | 309 |
Cores________________________________________________________ | 320 |
6 | 328 |
Nios II Processor Hardware Design ________________ | 352 |
Operating System Support for SOPC Design ____________________ | 374 |
The Electric Train Controller_____________ | 148 |
The µP 3 _________________________ | 170 |
VGA Video Display Generation using FPGAs ___________________ | 192 |
Laboratory Exercises | 210 |
Interfacing to the PS2 Keyboard and Mouse ___________________ | 214 |
Laboratory Exercises | 229 |
Generation of Pseudo Random Binary Sequences _______ | 391 |
LCD Panel Character Display | 392 |
Common IO Connector Pin Assignments ______________ | 397 |
| 407 | |
Other editions - View all
Rapid Prototyping of Digital Systems, Volume 1 James O. Hamblen,Michael D. Furman No preview available - 1999 |
Rapid Prototyping of Digital Systems, Volume 2 James O. Hamblen,Michael D. Furman No preview available - 2000 |
Common terms and phrases
additional assignments base BEGIN bits block Chapter character chip circuit clock color command compiled component configuration connected connector contains core counter cycle decode delay device direction display DOWNTO drive example execute FPGA board function gate hardware High implement initial input instruction interface keyboard logic machine memory MIPS module motor mouse move needed Nios II Nios II processor operation options output pixel port processor pulse pushbutton reset robot scan seen sensor serial servo shift shown in Figure signal simulation single SOPC specify speed standard statement STD_LOGIC STD_LOGIC_VECTOR stop switch synthesis Table track train turn Verilog VHDL window wire write
References to this book
Introduction to Embedded System Design Using Field Programmable Gate Arrays Rahul Dubey Limited preview - 2008 |