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Dependencies Among Instructions and Their Resolution
Code Scheduling and VLIW Machine Organizations
6 other sections not shown
adder algorithm alias analysis basic block benchmarks branch history table branch instruction branch prediction branch target buffer compaction compiler complete Computer Architecture concurrency conditional branch control flow cost data dependencies decode delayed branch dynamic effect entry example execution unit Figure floating-point functional units graph hardware hyperblock IEEE implementation instruction cache instruction execution instruction fetch instruction issue instruction stream instruction-level parallelism instructions per cycle iteration latency load logic loop memory microcode MOP's multiple node number of instructions operands operations optimizations path performance pipeline precise interrupts prediction bits prefetching Proc queue reduce register file register renaming reorder buffer reservation stations result RISC scheme Section sequence sequential simulation software pipelining speculative execution speedup stage static strategies superblock superpipelined superscalar superscalar processors taken branch target address techniques tion trace scheduling tree instruction unrolling vector VLIW window