FPGA Design Automation: A Survey

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Now Publishers Inc, 2006 - Technology & Engineering - 140 pages
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FPGA Design Automation: A Survey is an up-to-date comprehensive survey/tutorial of FPGA design automation, with an emphasis on the recent developments within the past 5 to 10 years. The focus is on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. FPGA Design Automation: A Survey can be used as both a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.
  

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Page 138 - VPR: A New Packing, Placement and Routing Tool for FPGA Research,
Page 146 - 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol.
Page 149 - S. Yamashita, H. Sawada, and A. Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications.
Page 138 - F. Assaderaghi. D. Sinitsky, SA Parke, J. Bokor, PK Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI", IEEE Transactions on Electron Devices.
Page 140 - Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays" , ACM Trans, on Design Automation of Electronic Systems, Vol.
Page 138 - V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs.
Page 137 - Circuits, 25, 1217-1225, 1990. [2] E. Ahmed and J. Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the Eighth International Symposium on FPGAs, 2000, pp.
Page 142 - LA. Entrena and K.-T. Cheng, Combinational and sequential logic optimization by redundancy addition and removal, IEEE Trans.
Page 148 - A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,
Page 145 - A. Marquardt, V. Betz, and J. Rose, Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density, Proceedings of the Seventh International Symposium on FPGAs, 1999, pp.

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