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Parallel Simulation of Heterogeneous Arithmetic Units Networks
DelayTime Bounds and Wave form Bounds for RLCG Ladder Networks
A Methodology for Evaluating Parallel
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application architecture assigned basic block behavior bids buffer checkpointing circuit communication compiled Computer connection constraints cycle data flow diagrams deadline defined delay described diagram digit DIPART distributed dot product dynamic entity environment equations error rate evaluation event example execution Foresight forward algorithm function graph hard real-time hardware I/O node IEEE implementation input instruction interconnection interface interval iteration load logic logic value machine memory method module MOSFET node object object-oriented operation optimization OSDL OTDD output packet parameters performance ports processor protocol provides queue redundancy request rollback router scheduling sequence server shown in Figure signal SimTool simulation software components SPARC specific SSGM strategy switch symbolic simulation system models target program task technique ternary logic time-step timestamp tion tool traffic variable VHDL VLSI voltage XPOSE