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ADD instruction ADD RO Anstruction in head block of instructions block size Block-based Dispatch Window branch instruction branch prediction Branch Target Buffer Circular Buffer combinational logic conditional fetch critical path cycles per instruction data dependency decode dependency information Dispatch Stack FDS Dispatch Window BDW DW II EX dynamic instruction stream EX EX EX EX WB execution stage Fast Dispatch Stack FIFO functional units gate delay implementation Improvement From Branch independent instructions instruction cache instruction fetch instruction in slot Instructions per Clock instructions per cycle intra-block dependency bits intra-block dependency evaluation Livermore Loops logic blocks longest number marked issued memory access MUL R2 multi-port register number of blocks number of cycles number of instructions operands performance prefetching processor RAW/WAW Dependency Field RAWAVAW register file reset RISC RU tables shown in Figure Simulation Results sink register source registers superscalar target block transistor count WAW dependencies window sizes Write RAW