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CONTENTS page CONTENTS page
Local IO EISA Support Peripheral LIO E 152
54 other sections not shown
A-BUS address bus Address Register asserted B-BUS BMIC burst cycles Bus Controller bus cycle bus master cache CHRDY clock command Compatible Configuration Register control signals Current data bus data transfers de-asserted DECODE SIGNALS Default device DRAM Controller driven active dword edge of BCLK EISA bus EISA master EISA slave EISA/ISA bus EXRDY external falling edge FIFO Figure function HCLK HCLKCPU HM/IO host bus host cycle Host Master HW/R iAPX inactive input interface internal interrupt request IOWC latch logic main memory master cycles memory cycle memory ownership memory write Micro Channel Mode Register MRDC MWTC Note open collector Output Enable Parallel Port Peek/Poke pin description PQFP processor programmed read cycle refresh cycles reset rising edge sampled SCLK Serial Port Setup snoop status STROBE synchronous system bus Timer Type write cycles