Superscalar microprocessor design
The term superscalar describes a computer architecture that achieves performance by concurrent execution of scalar instructions. Superscalar architectures represent the next step in the evolution of microprocessors. This book is intended as a technical tutorial and introduction for engineers & computer scientists. The book concentrates on reduced instruction set (RISC) processors.
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1:const 2:consth a_ptr Address Unit allocation antidependencies architecture basic block branch delay branch prediction central window chapter CISC compensation code computation critical path data cache decoded instructions dispatch stack example execution fetch floating-point fmul four-instruction decoder functional units future file general-purpose hardware history buffer implementation in-order issue initiation interval instruction decoder instruction fetcher instruction parallelism instruction runs instruction set instruction window instructions per cycle large number latencies load/store loads and stores logic lookahead loop iterations memory microcode microprocessors mispredicted branch Number of Entries number of instructions operands operations out-of-order issue output dependencies performance ports reduced register allocation register file register renaming register update unit reload reorder buffer reorder-buffer entry reservation stations reservation table resource conflicts restart RISC processors scalar processor scoreboarding software pipelining software scheduling Speedup stalls store buffer struction superpipelined superscalar processor tion trace scheduling true dependencies two-instruction decoder unrolled users VLIW yacc