ProceedingsComputer Society Press of IEEE, 2004 - Computer architecture |
Contents
K Olukotun Stanford University | 14 |
An Ultra LowPower Processor for Sensor Networks | 27 |
Storage | 37 |
Copyright | |
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abstract algorithm allocation analysis application asynchronous circuits bandwidth benchmarks bits block bricks buffer cache miss checkpoint chip chunk coherence decoupling commit compiler Computer Architecture configuration core D-SPTF dependence detection disk domain DVFS dynamic energy epoch erasure coding evaluate example execution Figure function graph gzip hardware helper thread HRTA IEEE implementation input instruction window International Symposium Itanium L2 cache layout leak load loop memory latency Microarchitecture Microvisor monitor nodes OpenMP operating system optimization overhead PALcode parallel performance permutation phase pipeline pointer prediction prefetching Proceedings processor Programming Languages protocol queue register file replication request requires scheduler scheme Section security tags sensor server Shear shows simulation slice SNAP/LE speculative speculative execution speedup stack static storage superscalar synchronization Table techniques throughput TinyOS tion trace transactions virtual machine workloads write