The Future of Test: International Test Conference, 1985 Proceedings, November 19, 20, 21, 1985 |
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Page 65
... Test counts propagated through an XOR gate The dual - ramp algorithm was developed to produce suffi- cient information for test generation and to minimize the toal sensitive count . The algotithm deals with the minimization of test counts ...
... Test counts propagated through an XOR gate The dual - ramp algorithm was developed to produce suffi- cient information for test generation and to minimize the toal sensitive count . The algotithm deals with the minimization of test counts ...
Page 68
... test counting which , as discussed earlier , does not precisely handle XOR and reconvergent fanouts . However , TMA results provide test counts for input leads of the fanout loop as well as for leads outside the fanout loop . Resolution ...
... test counting which , as discussed earlier , does not precisely handle XOR and reconvergent fanouts . However , TMA results provide test counts for input leads of the fanout loop as well as for leads outside the fanout loop . Resolution ...
Page 73
... test counts ; Figure 14. An example on test count matrices and test set Keeping the physical meaning of test count matrices in mind , test generation can be considered as an enumeration process that determines the right combinations of ...
... test counts ; Figure 14. An example on test count matrices and test set Keeping the physical meaning of test count matrices in mind , test generation can be considered as an enumeration process that determines the right combinations of ...
Contents
Keynote Speaker | 3 |
TEST CONFERENCE | 10 |
Test Generation System Directions | 39 |
Copyright | |
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Common terms and phrases
1985 International Test algorithm analysis applied Automatic Test Pattern Automation backtracking calibration cells chip circuit clock CMOS combinational cost cycle delay fault delay test detection device device under test diagnostics Digital equipment error example fanout fault coverage fault model fault simulation flip functional test gate delay GIPS hardware IEEE implementation instrument interface International Test Conference latch LFSR load logic logic value manufacturing measure memory method microprocessor node operation output Paper parameters PEAT performance port probability problem processor propagation random test reconvergent scan selected self-test sensitization sequence sequential sequential circuit shift register shown in Figure signal specific stuck-at faults Table techniques Teradyne test counts test length test pattern test program test system test vectors testability tester tion transistor transition VLSI voltage wafer watchdog XOR gate