ProceedingsIEEE Computer Society Press, 1984 - Computer storage devices |
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Page 135
... Signature A. Extended LFSR This enhancement is shown in figure 2. Since the error escape is related to the number of ... Signature Analysis Scheme T 4 CUT R m Fault - derived errors recovered 2mL 2o E Em 2 S with Enhancement Basic Scheme ...
... Signature A. Extended LFSR This enhancement is shown in figure 2. Since the error escape is related to the number of ... Signature Analysis Scheme T 4 CUT R m Fault - derived errors recovered 2mL 2o E Em 2 S with Enhancement Basic Scheme ...
Page 138
... signature - possibly of varying sizes - is obtained . In such cases the resulting signature can be viewed as a con- catenation of all observed signatures ; thereby , preserving the view that the signature analysis scheme is a function ...
... signature - possibly of varying sizes - is obtained . In such cases the resulting signature can be viewed as a con- catenation of all observed signatures ; thereby , preserving the view that the signature analysis scheme is a function ...
Page 341
... Signature analysis is the mechanism that reduces a large amount of data into a compressed representation of few bits known as a " signature " . The serial or parallel signature analyzers are based on the theory of polynomial division by ...
... Signature analysis is the mechanism that reduces a large amount of data into a compressed representation of few bits known as a " signature " . The serial or parallel signature analyzers are based on the theory of polynomial division by ...
Contents
Wm J Warwick Vice President Robert Albrow Chairman | 1 |
1 | 7 |
INTERNATIONAL | 8 |
Copyright | |
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1984 International Test algorithm applied array asynchronous automatic Automation block burn-in calibration cell channel chip circuit circuitry clock CMOS combinational complex components cost cycle D/A converter debugging detected device device under test diagnostic drive electronics error example execution failure fault coverage fault model fault simulation flip-flops frequency functional test gate hardware IEEE implemented in-circuit test input integrated circuits interface International Test Conference LFSR logic logic simulator machine measurement memory method microprocessor mode module multiplex nodes operation output Paper parameters path performance probe problem processor random sample scan self-test sequential signal signature soft errors strategy stuck-at faults Table techniques temperature Teradyne test engineer test patterns test program test sequence test set test system test vectors testability analysis tester tion transistor Verifier VLSI voltage wafer waveform