SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling (Google eBook)

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Springer Science & Business Media, Sep 15, 2006 - Computers - 448 pages
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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis. SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language. In addition, the second edition features a new chapter that explanis the SystemVerilog 'packages', a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
  

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Contents

SystemVerilog Procedural Statements
169
71 New operators
170
712 Assignment operators
173
713 Equality operators with dont care wildcards
176
714 Set membership operator inside
178
72 Operand enhancements
180
723 Size casting
181
724 Sign casting
182

212 Referencing package contents
10
213 Synthesis guidelines
14
221 Coding guidelines
17
224 Coding guidelines for importing packages into unit
19
225 Synthesis guidelines
25
23 Declarations in unnamed statement blocks
26
231 Local variables in unnamed blocks
27
24 Simulation time units and precision
28
242 Time values with time units
30
243 Scopelevel time unit and precision
31
244 Compilationunit time units and precision
32
25 Summary
34
SystemVerilog Literal Values and Builtin Data Types
36
31 Enhanced literal value assignments
38
32 define enhancements
39
322 Constructing identifier names from macros
41
33 SystemVerilog variables
42
332 SystemVerilog 4state variables
43
333 SystemVerilog 2state variables
44
334 Explicit and implicit variable and net data types
47
335 Synthesis guidelines
48
341 2state type characteristics
49
343 Using 2state types with case statements
51
35 Relaxation of type rules
52
36 Signed and unsigned modifiers
55
37 Static and automatic variables
56
371 Static and automatic variable initialization
59
372 Synthesis guidelines for automatic variables
60
373 Guidelines for using static and automatic variables
61
382 Initializing sequential logic asynchronous inputs
65
39 Type casting
67
392 Dynamic casting
69
393 Synthesis guidelines
70
310 Constants
71
311 Summary
72
SystemVerilog UserDefined and Enumerated Types
75
411 Local typedef definitions
76
413 Naming convention for userdefined types
78
42 Enumerated types
79
421 Enumerated type label sequences
83
423 Enumerated type values
84
424 Base type of enumerated types
85
425 Typed and anonymous enumerations
86
427 Casting expressions to enumerated types
88
428 Special system tasks and methods for enumerated types
89
429 Printing enumerated types
92
43 Summary
93
SystemVerilog Arrays Structures and Unions
94
51 Structures
96
511 Structure declarations
97
512 Assigning values to structures
98
513 Packed and unpacked structures
101
514 Passing structures through ports
104
515 Passing structures as arguments to tasks and functions
105
521 Unpacked unions
106
522 Tagged unions
108
523 Packed unions
109
524 Synthesis guidelines
111
53 Arrays
113
532 Packed arrays
116
533 Using packed and unpacked arrays
118
534 Initializing arrays at declaration
119
535 Assigning values to arrays
121
536 Copying arrays
123
537 Copying arrays and structures using bitstream casting
124
538 Arrays of arrays
125
539 Using userdefined types with arrays
126
5310 Passing arrays through ports and to tasks and functions
127
5311 Arrays of structures and unions
128
5314 An example of using arrays
129
54 The foreach array looping construct
130
55 Array querying system functions
132
56 The bits sizeof system function
134
57 Dynamic arrays associative arrays sparse arrays and strings
135
58 Summary
136
SystemVerilog Procedural Blocks Tasks and Functions
137
61 Verilog general purpose always procedural block
138
62 SystemVerilog specialized procedural blocks
142
622 Latched logic procedural blocks
150
623 Sequential logic procedural blocks
152
63 Enhancements to tasks and functions
153
633 Returning before the end of tasks and functions
154
634 Void functions
155
635 Passing taskfunction arguments by name
156
636 Enhanced function formal arguments
157
637 Functions with no formal arguments
158
639 Default formal argument values
159
6310 Arrays structures and unions as formal arguments
160
6311 Passing argument values by reference instead of copy
161
6312 Named task and function ends
165
6313 Empty tasks and functions
166
731 Local variables within for loop declarations
183
732 Multiple for loop assignments
185
734 Synthesis guidelines
186
741 Synthesis guidelines
188
761 The continue statement
190
763 The return statement
191
764 Synthesis guidelines
192
78 Statement labels
194
79 Enhanced case statements
195
791 Unique case decisions
196
792 Priority case statements
199
793 Unique and priority versus parallel_case and full_case
201
710 Enhanced ifelse decisions
203
7102 Priority if decisions
205
711 Summary
206
Modeling Finite State Machines with SystemVerilog
207
81 Modeling state machines with enumerated types
208
811 Representing state encoding with enumerated types
210
812 Reversed case statements with enumerated types
211
813 Enumerated types and unique case statements
213
814 Specifying unused state values
214
815 Assigning state values to enumerated type variables
216
816 Performing operations on enumerated type variables
218
82 Using 2state types in FSM models
219
83 Summary
221
SystemVerilog Design Hierarchy
222
91 Module prototypes
224
911 Prototype and actual definition
225
92 Named ending statements
226
93 Nested local module declarations
227
931 Nested module name visibility
230
932 Instantiating nested modules
231
933 Nested module name search rules
232
94 Simplified netlists of module instances
233
941 Implicit name port connections
238
942 Implicit port connection
242
95 Net aliasing
244
951 Alias rules
245
952 Implicit net declarations
246
953 Using aliases with name and
247
961 All types can be passed through ports
251
962 Module port restrictions in SystemVerilog
252
97 Reference ports
255
971 Reference ports as shared variables
256
98 Enhanced port declarations
257
983 SystemVerilog port declarations
258
99 Parameterized types
260
910 Summary
261
SystemVerilog Interfaces
263
101 Interface concepts
264
1011 Disadvantages of Verilogs module ports
268
1012 Advantages of SystemVerilog interfaces
269
1013 SystemVerilog interface contents
273
102 Interface declarations
274
1021 Source code declaration order
276
1032 Generic interface ports
278
105 Referencing signals within an interface
279
106 Interface modports
281
1061 Specifying which modport view to use
282
1062 Using modports to define different sets of connections
286
107 Using tasks and functions in interfaces
288
1071 Interface methods
289
1073 Synthesis guidelines for interface methods
292
1074 Exporting tasks and functions
293
108 Using procedural blocks in interfaces
296
1010 Verification with interfaces
298
1011 Summary
299
A Complete Design Modeled with SystemVerilog
300
112 Data abstraction
302
113 Interface encapsulation
305
squat
308
115 Receivers and transmitters
315
1152 Transmitter state machine
318
116 Testbench
321
117 Summary
327
Behavioral and Transaction Level Modeling
329
121 Behavioral modeling
330
123 Transaction level modeling in SystemVerilog
332
1231 Memory subsystem example
333
124 Transaction level models via interfaces
335
125 Bus arbitration
337
126 Transactors adapters and bus functional models
341
1262 Adapter in an interface
348
127 More complex transactions
353
128 Summary
354
The SystemVerilog Formal Definition BNF
355
Verilog and SystemVerilog Reserved Keywords
395
A History ofSUPERLOG the Beginning of SystemVerilog
401
Index
415
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