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2-way ACS unit 3-level 4-state 4-way ACS achieve ACS array ACS complexity ACS hardware area estimates area-efficient block Viterbi decoder Branch Metric Unit cascade architectures cascade chain cascade Viterbi decoder clock cycle clock rate CMOS convolutional code decode block decode rate decoded output digit encoder equivalent FCVD architecture fully parallel architectures given hardware complexity hardware utilization hence higher radix hybrid architectures input symbol intersymbol interference iteration rate latency lGb/s lookahead matrix matrix transpose maximum likelihood metric update minimized method multiple-input SRPs operation pretrace-back unit processing PTBU radix-2 ACS unit radix-2 fully parallel radix-2 PCVD architecture radix-2 trellis radix-4 ACS radix-4 architecture register-exchange SBVD method selftest sequence sequential shift register shortest path shown in Figure skew buffer sliding block decoder sliding block Viterbi soft decision inputs subtrellis survivor path length systolic SBVD architecture throughput trace-back unit transpose unit trellis iteration unified approach unified decomposition Vector Processor Viterbi algorithm