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MCM Tsting Bringing MCMs into
8 other sections not shown
algorithm analysis applied approach ASIC ATPG backplane BiCMOS boundary scan bridging faults checker clock CMOS components Computer cost cycle data paths delay test detected device diagnostic driver failure fault coverage fault model fault simulation fault-escape fault-free faulty circuit feedback functional graph hardware Iddq test IEEE implementation input pattern interconnects International Test Conference latch LFSR linear logic simulation logic value macro measurement memory method module node operation Paper polynomial primary outputs problem Proc propagation PSBM reduced scan chain scan design scan path scheme selected self-test sequential circuits shown in Figure signal signature strategy stuck-at fault Table techniques Test Conf TEST CONFERENCE 1992 test pattern test program test registers test schedule test sequence test session test set test system test units test vectors testability tester tion transistor transition Type I errors verification VLSI voltage