Architectures for Transactional MemoryStanford University, 2009 - 145 pages Architectures for transactional memory. |
Contents
The Architectures of | 2 |
Evaluation of HTM Design Space | 29 |
29 | 52 |
Copyright | |
2 other sections not shown
Common terms and phrases
32 CPUs abort abort handler architecture atomic bandwidth bayes benchmarks bits Bloom filter buffer cache line closed-nested CM policy coherence protocol commit handler commit scheme Commit Violate Stall conditional synchronization contention management continuous transactions cycles detect conflicts EP and LP EP-OLDEST evaluate Execution time breakdown false sharing genome hardware high contention Idle/Synch Validate Commit implement instructions interconnect intruder kmeans L1 Miss Memory labyrinth Lazy-Optimistic livelock LO-BASE locks LogTM mechanisms MESI Miss Memory Idle/Synch mp3d multicore nested transactions nesting level non-transactional Normalized Execution open-nested transactions Overflow L1 Miss overhead parallel pathologies performance pessimistic conflict detection processor programming languages read-set rollback scheduling Section semantics serializable speedup ssca2 STAMP applications STMs system calls TCC-BACK TCC-BASE TCC-UPDATE TCC-WORD thread tion TM design TM systems trans transactional memory two-phase commit undo log update vacation Validate Commit Violate Violate Stall Violate violation handler virtualization write-set yada