Proceedings: May 29 - 31, 1996, Santiago de Compostela, Spain |
Contents
Logic Design I | 10 |
New Interpolation Algorithms for MultipleValued ReedMuller Forms | 16 |
Family of Fast Mixed Arithmetic Logic Transforms for MultipleValued | 24 |
Copyright | |
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Common terms and phrases
algorithm application binary binary decision diagrams Boolean algebra Boolean functions cell circuit complete Computer consider decision diagrams defined Definition denoted elements equation example Figure finite func function f Fuzzy Logic gate Helena Rasiowa HEMT IEEE implementation inference lattice Lemma literal logic formula logic values matrix MOSFET multi-valued logic multiple multiple-valued functions Multiple-Valued Logic MV-algebras MVL function nonsingular number of nodes obtained OMDD operation output p-valued P₂ permutation polynomial power clock primary inputs problem Proc proof propositions quaternary Rasiowa realized recursive Reed-Muller Reed-Muller Expansion relation representation represented ROMDD rule sequent shown in Fig signal skew Boolean structure subset switching symmetric t-norms terminal nodes ternary ternary logic Theorem tion transform transistors truth degree truth values unary unary operations Valued Logic variables vector VHDL voltage x₁