System-level Test and Validation of Hardware/Software Systems (Google eBook)

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Springer Science & Business Media, Mar 30, 2006 - Technology & Engineering - 192 pages
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New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.
  

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Contents

Table of Figures
7
2 Representativeness of RTL gatelevel LSA faults and physical defects
18
A Symbolic Approach
26
1 HTD and ETD errors for a GAbased and a BDDbased ATPG
29
4 Laerte++ testbench
35
11 Sequence hierarchy
41
1 The pseudocode of the HLTG algorithm
52
4 The proposed processor customization and validation flow
60
4 PLASMA block diagram
95
Tackling Concurrency and Timing Problems
107
1 Synchronization in a producerconsumer example
112
3 AAL1 MTE fault coverage distribution
118
1 Cost calculation for hybrid BIST under 100 assumption
124
3 An example of a corebased system with independent BIST resources
130
7 Cost curves for a given core Ck
136
13 Iterative cost estimation
145

A Hierarchical Approach
67
1 A gatelevel circuit and its corresponding SSBDD
71
3 DIFFEQ benchmark with testability figures for every individual FU
77
Test Program Generation from Highlevel Microprocessor Descriptions
82
1 Qualitative description of the methodology
88
9
148
1 The FT for the storage system with hot spare memories
154
5 The MIF values for the components of the system with hot spares
166
Index
175
Copyright

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About the author (2006)

Matteo Sonza Reorda is the leader of the computer-aided design group of the Dipartimento di Automatica e Informatica, Politecnico di Torino. Zebo Peng is Professor of the chair in Computer Systems and Director of the Embedded Systems Laboratory at LinkAping University.