VHDL: Programming by Example* Teaches VHDL by example * Includes tools for simulation and synthesis * CD-ROM containing Code/Design examples and a working demo of ModelSIM |
Contents
| 1 | |
| 15 | |
Chapter 3 Sequential Processing | 39 |
Chapter 4 Data Types | 73 |
Chapter 5 Subprograms and Packages | 109 |
Chapter 6 Predefined Attributes | 143 |
Chapter 7 Configurations | 173 |
Chapter 8 Advanced Topics | 205 |
RTL Simulation | 329 |
Synthesis Results | 357 |
Chapter 16 Place and Route | 369 |
VITAL Simulation | 379 |
Chapter 18 At Speed Debugging Techniques | 399 |
Standard Logic Package | 413 |
VHDL Reference Tables | 435 |
Reading VHDL BNF | 445 |
Chapter 9 Synthesis | 231 |
Chapter 10 VHDL Synthesis | 251 |
Chapter 11 High Level Design Flow | 273 |
Chapter 12 TopLevel System Design | 289 |
Synthesis Description | 303 |
VHDL93 Updates | 449 |
Index | 469 |
About the Author | 477 |
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Common terms and phrases
ALIAS and2 and3 array ASIC ASSERT statement attribute BEGIN behavior BIT_VECTOR block boolean chapter clause clk_en clock compiled component instantiation compout configuration constant constraints contains CPU design create data_out debugger declaration section delay device dout downto ELSIF END COMPONENT END LOOP END PROCESS entity enumerated type executed flip-flop fourval FPGA gate good_val IEEE.std_logic_1164.ALL implement inout instruction INTEGER JTAG keyword l’LENGTH LIBRARY IEEE load logic LOOP statement muxval nanoseconds netlist next_state nineval opcode operation overloaded package body place and route PORT MAP procedure process statement qbus range Register Transfer Level reset resolution function result’RANGE LOOP result(i RETURN result RETURN std_ulogic_vector rising edge route tools shown in Figure signal assignment statement simulation specified std_logic std_logic_vector std_ulogic subprogram subtype synthesis tool testbench up_dwn VARIABLE result vector VHDL VHDL description WAIT statement xmap xnor