16-/32-bit Embedded Processor Handbook |
Contents
376 EMBEDDED PROCESSOR | 31 |
MEMORIES AND PERIPHERALS | 6-1 |
Chapter 7 | 7-6 |
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Common terms and phrases
80960 architecture active addressing modes AP-Bus asserted bits BUFFER burst Bus Controller bus cycle bus master byte or word Capacitance chip select CLK2 CLKIN CLKOUT clock cycle command configured control block control registers coprocessor data data deasserted debug device disp DMA channel DMA controller DMA transfer DT/R EPROM execution external fault float frame functions hardware HLDA HOLD HOLDA indicates input integer Intel interface internal interrupt controller interrupt request interrupt sources interrupt vectors L-Bus latched load LOCK logic Low insertion force MAX COUNT register maximum memory module Non-Maskable Interrupt offset on-chip One-X Opcode open-drain operands operation output Package Parameter performance peripheral Pin Grid Array PLCC pointer PQFP priority procedure provides READY register set register/memory RESET segment Setup signal specific stack synchronized Table Test timer types Voltage wait WAVEFORMS zero оо