Cost-effective Processor Design with an Application to Fast Fourier Transform Computers
Department of Electrical Engineering, Stanford University., 1973 - Algorithms - 334 pages
A cost-effective processor design is one that attains a high ratio of processing performance to processor component cost. This research investigates the circuit design of a processor or processing subsystems for costeffective implementation of a particular computation algorithm. The logic designs considered in this work use circuit components for which the delay and cost of functional building blocks or gates are known. A logic design technique is described that permits processing performance and cost comparisons among alternative computation algorithms and circuit technologies. It also provides a basis for contrasting alternative processor architectures, including both pipelined and parallel computing structures. (Modified author abstract).
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COSTEFFECTIVE PROCESSOR DESIGN
COSTEFFECTIVE DESIGN OF FAST FOURIER TRANSFORM
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adder modules adder Standard MSI ALU WITH LAC arithmetic and register arithmetic modules attained Attn balanced cordic algorithm best-value simple design bit-widths bottleneck segment carry-save adder cascade segment circuit design circuit modules circuit technologies component cost computation algorithm computation element computational sequence cost-effective design design goals design results design value digital filters factors fast adder Standard Fast Fourier Transform FFT algorithm FORTRAN full-butterfly Hanscom Field implementation value iteration Kalman filter KOPT latch registers maximum maximum-performance design maximum-value design MSI fast adder multiplexed nonpipelined number of pipeline operand parallel replication parameters performance and cost performance bottleneck performance per unit performance/cost pipeline stages pipelined cascade architecture processing architectures processing band processing bandwidth processing performance register cost register modules register slices relative Schottky ALU selected shown in Figure simple element simple-element stage cut set standard half-butterfly standard latch Standard MSI fast Stanford Research Institute subelement subroutine theoretical tion WALLACE TREE