Analysis of multi-megabyte secondary CPU cache memories
Abstract: "This dissertation investigates multi-megabyte secondary caches. In a multi-level cache hierarchy, secondary caches service processor memory references that cannot be serviced by smaller and faster primary caches. With faster processors and expanding main memories, a multi-megabyte cache is increasingly vital because it shields processor memory references from costly main memory accesses, even when the processor references a large address space. Multi-megabyte secondary caches allow processors to execute at the speeds they are capable of, even when there is a large processor-to-main-memory speed gap.
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Background and Cache Performance Analysis
Long Traces For Cache Analysis
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100 million instructions 16-megabyte cache 4-megabyte 4-way set-associative address space algorithm ATUM available page frames average basic block behavior block size block sizes cache configurations cache design cache misses cache performance careful mapping chapter coefficient of variation cold-start bias compression constant-bits CPU cache Cycles Per Instruction data cache direct-mapped cache direct-mapped secondary caches dissertation eliminates execution figure shows fraction full trace data hardware Hierarchical implementation included increase INITMR inter-miss kilobytes larger caches latency locality of reference long traces main memory access megabyte caches memory references memory system microcode miss frequencies miss ratio miss reduction MPI estimates Mult2 multi-megabyte caches multiprogrammed traces Multl node operating system page fault phases primary cache processor random real-indexed cache reduce referenced sample lengths SCPI Section set sampling set-associative cache smaller caches stored techniques time-sample tion trace buffer trace-driven simulation Tree unbiased virtual address virtual memory virtual page write-back