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A Uniform Optimization Technique for Offset Assignment Problems
Code Generation for Compiled BitTrue Simulation of DSP Applications
Addressing Optimization for Loop Execution Targeting DSP with AutoIncrementDecrement Architecture
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access graph address register allocation application approach ASIA-II behavior bit-true branch and bound bus-invert channel circuit clock cycle code sharing codesign communication communication protocols compiler components Computer constraints core cost data list data ordering datapath decoder delay Design Automation Conference Differential Evolution driver DTSE edge eDRAM embedded DRAM embedded systems encoding estimation example execution false path FPGA functional unit global hardware heuristic hierarchical high-level synthesis IEEE immediate values implementation input interface iteration latch LD-CELP logic loop mapping memory meta flow method methodology modules node offset assignment operations optimization overhead parameters partitioning performance probability Proc procedure processor protocol register allocation resource retargetable retargetable compilation scheduling algorithm sharing shown in Figure signal simulation solution specification stage step subtask superscalar target task techniques tion tool variables VHDL VLIW VLSI width