The Microarchitecture of Pipelined and Superscalar Computers

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Springer Science & Business Media, Apr 30, 1999 - Computers - 265 pages
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This book is intended to serve as a textbook for a second course in the im plementation (Le. microarchitecture) of computer architectures. The subject matter covered is the collection of techniques that are used to achieve the highest performance in single-processor machines; these techniques center the exploitation of low-level parallelism (temporal and spatial) in the processing of machine instructions. The target audience consists students in the final year of an undergraduate program or in the first year of a postgraduate program in computer science, computer engineering, or electrical engineering; professional computer designers will also also find the book useful as an introduction to the topics covered. Typically, the author has used the material presented here as the basis of a full-semester undergraduate course or a half-semester post graduate course, with the other half of the latter devoted to multiple-processor machines. The background assumed of the reader is a good first course in computer architecture and implementation - to the level in, say, Computer Organization and Design, by D. Patterson and H. Hennessy - and familiarity with digital-logic design. The book consists of eight chapters: The first chapter is an introduction to all of the main ideas that the following chapters cover in detail: the topics covered are the main forms of pipelining used in high-performance uniprocessors, a taxonomy of the space of pipelined processors, and performance issues. It is also intended that this chapter should be readable as a brief "stand-alone" survey.
  

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Contents

FUNDAMENTALS OF PIPELINING
1
12 A taxonomy of pipelines
3
13 Ideal performance of a pipeline
6
14 Impediments to ideal performance
8
15 Case studies
10
16 Summary
30
TIMING AND CONTROL OF PIPELINES
31
22 Clocksignal distribution
34
442 Dynamic prediction
104
443 Case studies
128
444 Summary
143
45 Predicated execution
144
46 Other solutions of the branching problem
146
47 Effect of instructionset architecture
148
48 Summary
150
DATA FLOW DETECTING AND RESOLVING DATA HAZARDS
151

23 Latch design
39
24 Structural hazards and sequencing control
43
25 Summary
45
HIGHPERFORMANCE MEMORY SYSTEMS
47
31 Memory interleaving
48
311 Basic principles
49
312 Addressing patterns
51
313 Case studies
53
32 Caches
58
321 Placement policies
59
322 Replacement policies
63
323 Fetch policies
64
324 Write policies
65
325 Performance
66
326 Case studies
73
33 Summary
81
CONTROL FLOW BRANCHING AND CONTROL HAZARDS
83
41 Pipeline length and location of control point
86
42 Latency reduction by instruction buffering
88
421 Types of instruction buffer
89
422 Case Studies
90
423 Comparison of instruction buffers
96
424 Summary
97
43 Static instructionscheduling
98
44 Branch prediction
101
441 Static and semistatic prediction
102
51 Types of data hazards
152
52 Implementing renaming
157
53 Fast resolution of true hazards
163
54 Case studies
167
55 Summary
183
VECTOR PIPELINES
185
61 Fundamentals
186
62 Storage and addressing of vectors
191
63 Instruction sets and formats
197
64 Programming techniques
198
65 Performance
203
66 Case studies
208
67 Summary
218
INTERRUPTS AND BRANCH MISPREDICTIONS
219
71 Implementation techniques for precise interrupts
221
712 Reorderbuffer
223
713 Historybuffer
224
714 Futurefile
226
715 Checkpointrepair
228
717 Other aspects of machinestate
229
718 Summary
231
72 Case studies
233
73 Summary
242
Bibliography
243
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