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LIST OF ILLUSTRATIONS
Z80 HARDWARE ORGANIZATION
30 other sections not shown
accumulator addition address bus arithmetic binary bit position Byte Codes called carry bit carry flag CB byte chapter contents data bus Data Flow decimal decremented Description device digits DJNZ eight-bit Example execution Exercise FD byte fetch flowchart following the opcode Format Function hexadecimal high order HL register pair Implicit incremented index register Indirect input input/output interrupt IY register jump LD HL location immediately following loop low order memory location addressed memory location immediately MHz Addressing Mode microprocessor multiplication NOADD OBJECT CODE offset value one's complement opcode operand operation output P/V N C no effect parity program counter representation represented reset result is stored Rotate S Z H P/V N C shift shown in Figure specified register stack pointer subroutine subtraction symbolic tion two's complement usec zero