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Compression Technique for Interactive BIST Application
Robust and LowCost BIST Architectures for Sequential Fault Testing
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algorithm analysis applied approach architecture area overhead at-speed ATPG benchmark circuits bijection bits capacitances chip clock CMOS column combination compactor compression Computer Computer-Aided Design coupled cell coupling faults crosstalk crosstalk defect cycles delay faults detect diagnosis encoding example experimental results fanout fault coverage fault effects fault model fault simulation flash memories flip flip-flop flops FMA tests frequency function Golomb codes hardware IEEE IEEE Trans implementation interconnect International Test Conference IP cores LFSR logic march elements march tests memory method methodology minvdd module multiple node on-chip operation partial reset partition path primary input primary outputs Proc propagation proposed ramp sampling scan chains scan wheel scheme Section self-test sequence sequential circuits shown in Figure shows signal stuck-at faults system-on-a-chip Table technique Test Conf test data test mode test patterns test set test vectors testability tester tion transistor VLSI voltage