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REAL MODE ARCHITECTURE 431
FUNCTIONAL DATA 460
16 other sections not shown
386 DX Microprocessor 82396SX Smart Cache active LOW address bus asserted breakpoint bus cycle bus master byte enables Cache Directory cache read cacheable capacitive channel CLK2 clock CPUCLK2 cycle definition data bus decoded descriptor device DMA Controller DRAM drives DX CPU execution F2 Mode Figure function Gate High hit cycles HLDA inactive indicates input instruction interface interrupt request ISA bus latched Line Fill lntel386 DX lntel386 SL CPU lntel386 SX Microprocessor Load LOCK main memory non-cacheable non-pipelined Note opcode operand operation output page fault pipelined PQFP privilege level processor programmed Protected Mode read cycles read hit read miss READY READYO Real Mode refresh RESET SBRDY selector SHOLD signal Specifications SRAM SRDY SYSCLK System Bus Table TAG Valid bit timer transfer updated Valid Delay Virtual 8086 Mode wait write cycles