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acknowledge cycles address bus address decoder address latches address pipelining associative cache bits block buffers bus arbiter bus control logic bus cycle bus interface bus master Byte Enables cache controller chip select circuit CLK cycle CLK2 period clock data bus data transceivers data transfer delay direct mapped cache doubleword DRAM dual-port RAM DX CPU DX math coprocessor DX microprocessor data DX microprocessor system eprd EPROM frequency hardware I/O devices idle iLBX impedance input instruction inta Intel Intel386 DX microprocessor Intel387 DX math interrupt acknowledge Interrupt Controller interrupt request interrupt-acknowledge cycle INTR iowr iPSB M/IO main memory megabytes memory access microprocessor local bus MULTIBUS nanoseconds non-pipelined number of wait operation output pclk performance pins PLD RegOut Max processor Programmable Interrupt Controller read cycle READY refresh cycle RESET sampled shown in Figure SRAM subsystem system bus termination valid wait-state write cycle