## MOSFET MODELING FOR VLSI SIMULATION: Theory and Practice (Google eBook)A reprint of the classic text, this book popularized compact modeling of electronic and semiconductor devices and components for college and graduate-school classrooms, and manufacturing engineering, over a decade ago. The first comprehensive book on MOS transistor compact modeling, it was the most cited among similar books in the area and remains the most frequently cited today. The coverage is device-physics based and continues to be relevant to the latest advances in MOS transistor modeling. This is also the only book that discusses in detail how to measure device model parameters required. |

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### Contents

1 | |

15 | |

MOS Transistor Structure and Operation | 69 |

MOS Capacitor | 121 |

Threshold Voltage | 167 |

MOSFET DC Model | 230 |

Dynamic Model | 325 |

Modeling HotCarrier Effects | 366 |

Data Acquisition and Model Parameter Measurements | 402 |

Model Parameter Extraction Using Optimization Method | 501 |

SPICE Diode and MOSFET Models and Their Parameters | 536 |

Statistical Modeling and WorstCase Design Parameters | 563 |

Appendix A Important Properties of Silicon Silicon Dioxide and Silicon | 580 |

Appendix G Linear Regression | 587 |

List of Widely Used Statistical Package Programs | 599 |

### Common terms and phrases

approximation bias bulk charge C-V curve calculated channel devices channel length charge Qs circuit models circuit simulation CMOS Computer-Aided Design current Ids degradation depletion region depletion width diffusion diode dopant doping doping profile drain current drain end drain voltage effect electric field equation experimental factor function gate current gate oxide given by Eq holes hot-carrier IEEE IEEE Trans implant increases interface inversion layer ionization linear region linear regression long channel measured method minority carrier mobility model parameters MOS capacitor MOS transistor MOSFET model n-channel nMOST normally obtained optimization overlap capacitance oxide thickness p-type pMOST pn junction Poisson's equation polysilicon gate resistance saturation region semiconductor short-channel shown in Figure silicon slope Solid-State Electron source and drain source/drain SPICE strong inversion substrate current subthreshold threshold voltage transconductance Vdsat versus VLSI weak inversion zero

### Popular passages

Page 13 - General optimization and extraction of 1C device model parameters', IEEE Trans.

Page 2 - LOGIC <a) 1960 1970 1980 1990 10 2000 Fig. 1.1 (a) Exponential growth of the number of components on the chip (SSI = small-scale integration; MSI = medium-scale integration; LSI = large-scale integration; VLSI = very large-scale integration); (b) Exponential decrease of the minimum device dimensions. Dotted lines are projections. (From Sze [4, p. 3], slightly modified) Unfortunately not all device parameters can be scaled proportionately. These limits on scaling have increased the importance of device...