Proceedings: driving down the cost of test : October 21-25, 1995 Sheraton Washington Hotel Washington, D.C. USA.
Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers. Computer Society. Test Technology Technical Committee, IEEE Computer Society. Test Technology Technical Committee, Institute of Electrical and Electronics Engineers. Philadelphia Section
ITC, 1995 - Computers - 1011 pages
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INTRODUCTORY SECTION Table
User Application of Statistical Process Monitor Techiques
35 other sections not shown
algorithm analog analog circuits analysis applied approach array ASIC ATPG behavior block boundary scan bridging faults cache cell chip circuitry clock CMOS compared component Computer cost cycle debug device DUT board error failure fault coverage fault free fault model fault simulation fault-free flip-flops functional test gate hardware Iddq test IEEE IEEE Trans implementation input insertion Integrated Circuits International Test Conference latch logic measurement memory methodology mode module monitor multiple netlist node observability operation output Paper parallel parameters partial scan partitioning path delay faults performance problem Proc procedure processor propagation random scan chain Section selected sequence sequential circuits shown in Figure signal stuck-at faults substrate Table technique Test Conf test pattern test points test set test vectors testability tester tion tool transistor transition VLSI voltage waveform