Intel486 SL Microprocessor Superset Programmer's Reference Manual |
Common terms and phrases
82360SL configuration space address space area of memory auto power base address BIOS bit bit bit is set BITS 15 buffer strength bus cycles bus unit configuration cache cacheable Configuration Register Control Register CPU cache CPU clock CPU RESET CPUPWRMODE register deasserted LOW decoding device disabled disk DMA Channel DMA controller DRAM enable bit external bus unit field Flash BIOS Flash memory global standby I/O address I/O trap idle timer INDEX Intel486 SL CPU interrupt request ISA-bus Kbytes mask bit Mbytes MCBANK mode on-board memory controller parallel port PI bus power management power-on default value power-on reset programmed PWRGOOD signal Register Bits register is reset request bit Reserved Bit signal is deasserted SL microprocessor SL SuperSet SM-RAM SMI request Status Register stop break event suspend refresh suspend warning timer SYSCLK system event system management System Management Interrupt Timer Count unit configuration space watchdog timer write