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of VLSI Multichip Modules
Test Generation and Fault Simulation
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algorithm applied array bit-sliced block bridging faults chip clock clock signals CMOS combinational logic cost cross-point datapath decoder delay Design Automation diagnostic digital circuit elements error latency example failure fanout fault coverage fault detection fault list fault simulation feedback Figure flip-flop hardware IEEE IEEE Trans implementation input pattern input pin input vector instruction integrated circuits latch logic circuit logic design logic gate logic network logical value LSSD machine memory method microprocessor module NAND nodes number of faults operation parallel partitioning path performed primary inputs primary output problem Programmable Logic Array propagate pseudorandom random patterns random test scan scan/set self-test sensitized shift register shown in Fig signal single stuck-at fault storage structure stuck faults stuck-at fault stuck-open faults subsystem switch Table technique test mode test pattern test sequence test set testability tester tion transistor VLSI