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High Speed Machine Characteristics
Parallel and Vector Algorithm Organization
5 other sections not shown
2's complement ADD XINC.APTR algorithm APSTATUS arithmetic array atom bit-reverse clock column CYBER data pad bus data word device address dihedral angles DMA transfers dot product DPBS DPX<MD ECEPP execution exponent FADD FADDR fetch field Figure fixed-point flag floating point floating-point floating-point number FMUL FMULR format FORTRAN hardware host computer host CPU host interface host memory I/O device INCDPA INCMA incremented inner loop instruction cycle instruction word integer interrupt IODRDY LDAPS loaded main data memory mantissa matrix memory address register MFLOPS MNEMONIC mode OCTAL op-codes operands output OXOX panel performance pipeline PNLBS problem refer to note reset result s-pad s-pad operation scalar scalar processor SETMA SP(SPD sparse sparse matrix specified SPFN status register storage stored subroutine supervisor table memory TMRAM vector length vector processor zero