Statistical Analysis and Optimization for VLSI: Timing and Power

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Springer Science & Business Media, Jun 21, 2005 - Technology & Engineering - 279 pages
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Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest research in statistical timing and power analysis techniques is included, along with efforts to incorporate parametric yield as the key objective function during the design process. Included is the necessary mathematical background on techniques which find widespread use in current analysis and optimization. The emphasis is on algorithms, modeling approaches for process variability, and statistical techniques that are the cornerstone of the probabilistic CAD movement. The authors also describe recent optimization approaches to timing yield and contrast them to deterministic optimization. The work will enable new researchers in this area to come up to speed quickly, as well as provide a handy reference for those already working in CAD tool development.

  

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Contents

Introduction
1
11 Sources of Variations
2
113 Modeling Variations
3
114 Other Sources of Variations
4
122 Intradie Variations
5
13 Impact on Performance
9
Statistical Models and Techniques
13
21 Monte Carlo Techniques
14
43 HighLevel Statistical Analysis
138
44 GateLevel Statistical Analysis
140
441 Dynamic Power
141
442 Leakage Power
142
443 Temperature and Power Supply Variations
158
Yield Analysis
165
51 HighLevel Yield Estimation
168
512 Frequency Binning
175

211 Sampling Probability Distributions
19
22 Process Variation Modeling
24
222 Principal Components Based Modeling
28
223 Quad Tree Based Modeling
32
224 Specialized Modeling Techniques
34
23 Performance Modeling
42
232 NonNormal Performance Modeling
46
233 Delay Modeling
54
234 Interconnect Delay Models
59
235 ReducedOrder Modeling Techniques
67
Statistical Timing Analysis
79
31 Introduction
80
32 BlockBased Timing Analysis
83
321 Discretized Delay PDFs
84
322 Reconvergent Fanouts
88
323 Canonical Delay PDFs
98
324 Multiple Input Switching
110
33 PathBased Timing Analysis
114
34 ParameterSpace Techniques
118
342 Ellipsoid Method
120
343 CaseFile Based Models for Statistical Timing
122
35 Bayesian Networks
127
Statistical Power Analysis
133
41 Overview
134
42 Leakage Models
136
513 Yield Computation
176
52 GateLevel Yield Estimation
181
521 Timing Analysis
183
522 Leakage Power Analysis
185
523 Yield Estimation
187
53 Supply Voltage Sensitivity
194
Statistical Optimization Techniques
203
61 Optimization of Process Parameters
205
611 Timing Constraint
208
612 Objective Function
210
613 Yield Allocation
212
62 Gate Sizing
222
621 Nonlinear Programming
225
622 Lagrangian Relaxation
227
623 Utility Theory
229
624 Robust Optimization
235
625 SensitivityBased Optimization
240
63 Buffer Insertion
245
631 Deterministic Approach
246
632 Statistical Approach
247
64 Threshold Voltage Assignment
250
642 Dynamic Programming
260
References
265
Index
277
Copyright

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About the author (2005)

Ashish Srivastava received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur in 2001 and the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor in 2003. He is currently pursuing the Ph.D. degree at the University of Michigan, Ann Arbor. In summe r 2003 he was with the Technology CAD Division, Intel Corporation, Hillsboro, where he was a Graduate Intern and in summer 2004 he was with the Austin Research Lab, IBM, where he worked on leakage power optimization techniques . He is a recipient of the Intel PhD Fellowship, 2004. His research interests include optimization and statistical techniques for low-power VLSI design.

Dennis Sylvester received the B.S. degree in electrical engineering summa cum laude from the University of Michigan, Ann Arbor, in 1995. He received the M.S. and Ph.D. degrees in electrical engineering from University of California, Berkeley, in 1997 and 1999, respectively. He worked at Hewlett-Packard Laboratories in Palo Alto, CA, from 1996 to 1998. His dissertation research was recognized with the 2000 David J. Sakrison Memorial Prize as the most outstanding research in the UC-Berkeley EECS department. After working as a Senior R&D Engineer in the Advanced Technology Group of Synopsys, Mountain View, CA, he is now an Assistant Professor of Electrical Engineering at the University of Michigan, Ann Arbor. He has published numerous articles in his field of research, which includes the modeling, characterization, and analysis of on-chip interconnect, low-power circuit design and design automation techniques, and variability-aware circuit approaches. Dr. Sylvester received an NSF CAREER award, the 2000 Beatrice Winner Award at ISSCC, two outstanding research presentation awards from the Semiconductor Research Corporation, and a best student paper award at the 1997 International Semiconductor Device Research Symposium. He is the recipient of the 2003 ACM SIGDA Outstanding New Faculty Award and the 1938E Award for teaching and mentoring, which is the highest award given to a junior faculty in the Michigan College of Engineering. He has served on the technical program committee of numerous design automation and circuit design conferences and was general chair for the 2003 ACM/IEEE System-Level Interconnect Prediction (SLIP) Workshop. In addition, he helps to define the circuit and physical design roadmap as a member of the International Technology Roadmap for Semiconductors (ITRS) U.S. Design Technology Working Group. He is a member of IEEE, ACM, American Society of Engineering Education, and Eta Kappa Nu.

David Blaauw received his B.S. in Physics and Computer Science from Duke University in 1986, his M.S. in Computer Science from the University of Illinois, Urbana, in 1988 and his Ph.D. in Computer Science from the University of Illinois, Urbana, in 1991. He worked at the Engineering Accelerator Technology Division, IBM Corporation, Endicott, as a Development Staff Member, until August 1993. From 1993 till August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of t he High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan as an Associate Professor. His work has focused on VLSI design and CAD with particular emphasis on circuit analysis and optimization problems for high performance and low power designs. He was the Technical Program Chair and General Chair for the International Symposium on Low Power Electronic and Design in 1999 and 2000, respectively, and was the Technical Program Co-Chair and member of the Executive Committee the ACM/IEEE Design Automation Conference in 2000 and 2001.