Towards One-Pass Synthesis

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Springer Science & Business Media, May 31, 2002 - Computers - 181 pages
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The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since originally the complete process was too complex, it has been split up in several - more or less independent - phases. In the last 40 years powerful algorithms have been developed to find optimal solutions for each of these steps. However, the interaction of these different algorithms has not been considered for a long time. This leads to quality loss e.g. in cases where highly optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, like area and delay, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, some years ago the idea of one-pass synthesis came up. There were two main approaches how to guarantee that a design got "first time right": Combining levels that were split before, e.g. to use layout information already during the logic synthesis phase; Restricting the optimization in one level such that it better fits to the next one. So far, several approaches in these two directions have been presented and new techniques are under development. In Towards One-Pass Synthesis we describe the new paradigm that is used in one-pass synthesis and present examples for the two techniques above. Theoretical and practical aspects are discussed and minimization algorithms are given. This will help people working with synthesis tools and circuit design in general (in industry and academia) to keep informed about recent developments and new trends in this area.
  

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Contents

INTRODUCTION
1
PRELIMINARIES
7
22 Decomposition of Boolean Functions
9
23 Symmetric Functions
10
24 Logic Circuits
11
25 Testability
12
DECISION DIAGRAMS
19
32 Binary Decision Diagram
22
CIRCUITS DERIVED FROM DECISION DIAGRAMS
71
61 Direct Mapping of Decision Diagrams
72
62 Area Minimization
78
63 Testability
84
64 Delay Minimization
99
65 Summary and Future Directions
109
TECHNOLOGY DEPENDENT SYNTHESIS
113
71 Problem Formulation
114

33 Extensions of Binary Decision Diagrams
24
34 Reduction Concepts
28
35 Operations on Decision Diagrams
30
CLASSICAL SYNTHESIS APPROACHES
35
41 Transformations to Logic Networks
36
42 Functional Decomposition
40
43 Redundancy Addition and Removal
41
44 Spectral Techniques
42
46 Summary
43
EXACT MINIMIZATION
45
51 Exact Minimization
46
52 Extensions
54
53 Generation of Universal Logic Modules
55
54 Experimental Results
62
55 Summary and Future Directions
67
72 Combining Logic Synthesis and Technology Mapping
115
73 Delay Minimization
123
74 Experimental Results
127
75 Summary and Future Directions
134
LAYOUT DRIVEN SYNTHESIS
137
81 PseudoSymmetric Decision Diagrams
139
82 Lattice Synthesis Method
144
83 Lattice Trees
149
84 Experimental Results
151
85 Testability
154
86 Summary and Future Directions
159
CONCLUSIONS
161
REFERENCES
163
INDEX
177
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About the author (2002)

Prof. Rolf Drechsler has authored and edited numerous books for Springer