The Future of Test: International Test Conference, 1985 Proceedings, November 19, 20, 21, 1985 |
Contents
Plenary Session 12 VLSI Test SystemsSolutions to Session Chairmen | 1 |
Robert E Anderson Chairman Contents | 3 |
xxii | 10 |
Copyright | |
40 other sections not shown
Common terms and phrases
1985 International Test algorithm analysis applied Automation BILBO modules calibration cell chip circuit clock CMOS combinational component cost cycle debugging decoder delay fault developed device device under test diagnostics Digital error example fanout fault coverage fault model fault simulation functional test GIPS hardware IEEE implementation integrated circuit interface International Test Conference load logic logic value measurement memory method microprocessor mode multiple multiplexing node operation Paper parameters partition performance pin groups port problem Proc procedure processor Programmable Logic Arrays propagation random scan path selected self-test sequence sequential shift register shown in Figure signal signature specific stuck-at faults Table technique temperature Teradyne test counts test pattern test program test set test system test vectors testability tester tion transistor transition verify VLSI voltage waveforms