Test and Evaluation of the Generalized Gate Logic System SimulatorLangley Research Center, 1991 - 20 pages |
Common terms and phrases
14 LINCON runs arithmetic logic unit average latency clock cycles coincident error combinatorial logic comparison monitoring system coverage factors detected by MATMUL detected faults digital computer systems distinguishable faults eight program iterations estimate evaluate failed to produce fault simulator fault-tolerant digital computer fault-tolerant system faults detected faults that failed floating-point Gate Logic System gate-level GGLOSS simulation good-machine signature implementation Injected faults input iteration of LINCON laboratory prototype Langley Research Center latent faults LINCON program Logic System Simulator loop LOOP1 majority of faults McGough microcode microprocessor design microsequencer MicroVAX MISR NASA netlist number of faults percent produce an answer program iteration proportion proportion of distinguishable proportion of faults prototype hardware pseudorandom R_EXIT_1 R1_ELSE Run2 Run4 Run6 Run7 Rung Runi Runj S-GGLOSS study self-test simulated faults simulation results simulation strategy Simulator GGLOSS stuck-at faults SUBROUTINE Swern Table TEMPK TEMPM TEMPX RESULT tion undetected unfaulted voting frame