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Implementing Register Interlocks in ParallelPipeline Multiple
NonConsistent Dual Register Files to Reduce Register Pressure
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algorithm allocation applications array average bandwidth barrier synchronization benchmarks bits Bus-Expander bytes cache block cache coherence cache line cache miss cache pollution compiler Computer Architecture context switch cycle destage destination direct-mapped cache efficient evaluation execution fault fetch Figure flit functional units hardware hit ratio IEEE implementation improvement increase input instruction Kbytes latency loop machine mapped memory access memory modules memory system mesh miss ratio MP3D multiple multiprocessor node non-blocking loads on-chip operating system optimization overhead parallel performance physical pipeline prefetching processor queue R-tag cache reduce references register file register renaming request RISC scheduling scheme sequential prefetching set-associative cache shared memory SIMD Simple COMA simulation slots snarfing spatial locality speculative execution stream buffers subblock subnetwork subtree superscalar techniques thread throughput tion traffic vector virtual cache virtual channels workloads write