Proceedings |
Contents
The Semantics of Timing Constructs in Hardware Description | 10 |
Concepts in TestingI | 19 |
Characteristics of Statistical Fault Analysis | 24 |
Copyright | |
35 other sections not shown
Common terms and phrases
algorithm analysis architecture array behavior block buffer cache cell circuit clock CMOS complexity Computer concurrent connected constraints cycle database datapath decoder delay Design Automation Conference detection device error evaluation execution fault coverage fault simulation fault-free Fault-Tolerant FPU chip function GaAs gate global graph hardware IEEE IEEE Trans implementation input instruction Integrated Circuits interconnect interface latch layout linear logic machine matrix memory microcode microprocessor MicroVAX minimize module MOSFET multiple NMOS node operation optimization output package parallel partitioning path performance pipelined placement problem Proc processor RISC router routing segment sequence shown in Figure signal silicon simulated annealing specification STAFAN structure switch systolic systolic array techniques tion transistors tuple unit UNIX vector VLSI VMEbus voltage wiring