ULSI Process Integration 6, Issue 7

Front Cover
The Electrochemical Society, 2009 - Integrated circuits - 533 pages
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ULSI Process Integration 6 covers all aspects of process integration. Sections are devoted to 1) Device Technologies, 2) Front-end-of-line integration (gate stacks, shallow junctions, dry etching, etc.), 3) Back-end-of-line integration (CMP, low-k, Cu interconnect, air-gaps, 3D packaging, etc.), 4) Alternative channel technologies (Ge, III-V, hybrid integration), and 5) Emerging technologies (CNT, graphene, polymer electronics, nanotubes).
  

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Contents

Modeling Techniques for Strained CMOS Technology
3
Integration Challenges and Opportunities of Nanoelectronic Devices
19
Technology Evolution of Silicon NanoElectronics
33
Bio Inspired Architectures in the Nanoscale Integration Era
49
A Roadmap for NanoCMOS
67
Multigate Devices for High Performance Ultra Low Power and Memory
77
Ultrathin Body Effects in Multiple Gate SOI Transistors
91
Optical and Electrical Characterizations of Defects in SiGeoninsulator
99
Integration of New Materials for
291
Electrochemical Processes for the Production of Copper Interconnects on Non
303
Metal CMP Optimization Based on Chemically Formed Thin Film Analysis
315
Comparison of the Electrochemical Polishing of Copper and Aluminum in Acid
327
High Quality Virtual Substrates for Ge pMOS and IIIV nMOS
335
Challenges and Progress in GermaniumonInsulator Materials and Device
351
Comprehensive Study of the Fabrication of SGOI Substrates by the Ge
363
PtGe SchottkyBarrier Reduction by Rapid Thermal Diffusion of P Dopants
377

Very High Performance CMOS on Si551 Surface using Radical Oxidation
115
Variability Headaches in Sub32 nm CMOS
131
LowPower SiGe HBT and Circuit Technology for Future QuasiMillimeterWave Wireless Communications
137
From Silicon Nanocrystals to Molecular
151
Novel OmegaShapedGated TFT SONOS Memory
163
Overwhelming the 0 5 nm EOT Level for CMOS Gate Dielectric
171
Atomically Controlled CVD Processing for Doping of SiBased Group IV
177
Lowtemperature Oxidation of Semiconductor Surfaces by use of a Novel
185
C nMOSFETs
193
SiGe SEG Growth for Buried Channels pMOS Devices
201
Carbon SourceDrain Stressors Integration of a Novel Nickel Aluminide Silicide and PostSolidPhaseEpitaxy Anneal for Reduced SchottkyBarrier and
211
Stress Characterization of Selective Epitaxial Si1xGex Deposition for Embedded
217
Atomically Controlled Plasma Processing for Epitaxial Growth of Group IV
229
Lowfrequency Noise Analysis of the Impact of an LaO Cap Layer in
237
Integration Challenges in Standard CMOS with Multiple Gate Oxide Thicknesses J J Naughton and J Towner
247
Analysis of Remote Coulomb Scattering Limited Mobility in MOSFET with
253
Fast Detrapping Transients in HighK Dielectric Films
259
Charge Trapping Non Volatile Memory
269
The Effect of Material and Process Interactions on BEOL Integration
279
Development of IIIV MOSFET Process Modules Compatible with Silicon ULSI Manufacture
385
High Performance InGaAs MOSFETs with High Mobility using InP Barrier
397
Dopant Segregated Schottky DSS SourceDrain for Germanium pMOSFETs
405
Quasiballistic Transport of Charge Carriers in Nanometer FETs in the Model of
411
Computation from Devices to System Level Thermodynamics
421
Charge Storage Characteristics of Hybrid Nanodots Floating Gate
433
Emerging NonVolatile Memories by Exploiting Redox Reactions on the
441
Annealing Reaction for Ni Silicidation of Si Nanowire
447
Tunnel FieldEffect Transistors for Future LowPower NanoElectronics
455
Physics of Nanocontact between Si Quantum Dots and Inversion Layer
463
3D Suspended Nanowires Integration for CMOS and Beyond
471
Physics of NanoInterfaces and NanoStructures for Future Si NanoDevices
479
Electrothermal Transport in Carbon Nanostructures
487
Systhesis and Devices of Graphene
495
Novel Materials and Integration Schemes for CMOSBased Circuits for Flexible
503
Organic Semiconductor Lasers
513
H Gate Layer on Electron
525
Author Index
531
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