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32 bits 64 bits achieved Add/subtract algorithms applications arithmetic array processor bandwidth calculations central memory channel chips circuits clock period complex Cray Research Cray X-MP Cyber decimal delivered devices discs double precision equations example execution exponent FACOM fast faster floating point floating-point floating-point numbers FORTRAN compiler Fujitsu functional units GFLOPS grid hardware Hitachi ILLIAC IV input/output instruction buffer instruction stack integer language logic loop MASK Mbyte MFLOPS million 64-bit words million words module multiple Mwords NEC SX-2 ns clock operands optimization package parallel peak performance problem processing queue register file scalar processor sequential silicon simulation solve speed speedup statement storage stored subroutine subscript subsystem supercomputers switching synchronous tion transfer rate variables vector instruction vector length vector operations vector pipes vector processor vector registers vectorizable
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Krste Asanovic - 1998
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David C O'Neal - 1990 - Journal of Scientific Computing
Supercomputers and their Use The Theory of the Riemann Zeta ...
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