Digital Computer Arithmetic Datapath Design Using Verilog HDLThis text presents basic implementation strategies forarithmetic datapath designs and methodologies utilized in the digitalsystem. The author implements various datapath designs for addition, subtraction, multiplication, and division. Theory is presented toillustrate and explain why certain designs are chosen. Eachimplementation is discussed in terms of design choices and howparticular theory is invoked in the hardware.Along with the theory that emphasizes the design in question, Verilogmodules are presented for understanding the basic ideas that accompanyeach design. Structural models are implemented to guarantee correctsynthesis and for incorporation into VLSI schematic-capture programs.From the modules, the reader can easily add or modify existing code tostudy current areas of research in the area of computer arithmetic.The emphasis is on the arithmetic algorithm and not the circuit. Forany design, both algorithmic and circuit trade-offs should be adheredto when a design is under consideration. Therefore, the idea is toimplement each design at the RTL level so that it may be possiblyimplemented in many different ways (i.e. standard-cell orcustom-cell). Thus, professionals, researchers, students, and thosegenerally interested in computer arithmetic can understand howarithmetic datapath elements are designed and implemented.Also included is a CD-ROM which contains the files discussed in thebook. The CD-ROM includes additional files utilized in preparing thedesigns in Verilog including scripts to automatically generate Verilogcode for parallel carry-save and tree multipliers. Each Verilogdesign also contains each module including testbenches to facilitatetesting and verification. |
Contents
MOTIVATION | 1 |
Main Objective | 2 |
13 Datapath Design | 3 |
VERILOG AT THE RTL LEVEL | 7 |
22 Naming Methodology | 10 |
221 Gate Instances | 11 |
222 Nets | 12 |
224 Connection Rules | 13 |
45 Truncated Multiplication | 71 |
46 Twos Complement Multiplication | 78 |
47 SignedDigit Numbers | 82 |
48 Booths algorithm | 86 |
481 Bitwise Operators | 87 |
49 Radix4 Modified Booth Multipliers | 89 |
491 Signed Radix4 Modified Booth Multiplication | 91 |
410 Fractional Multiplication | 92 |
225 Vectors | 14 |
227 Nested Modules | 15 |
the Test Bench | 16 |
231 Test Benches | 18 |
24 Other Odds and Ends within Verilog | 19 |
242 Replication | 21 |
For Whom the Bell Tolls | 22 |
252 EventBased Timing | 23 |
26 Synopsys Design Ware Intellectual Property IP | 24 |
28 Summary | 26 |
ADDITION | 27 |
31 Half Adders | 28 |
33 Ripple Carry Adders | 30 |
34 Ripple Carry AdderSubtractor | 31 |
341 Carry Lookahead Adders | 34 |
3411 Block Carry Lookahead Generators | 36 |
35 Carry Skip Adders | 40 |
351 Optimizing the Block Size to Reduce Delay | 42 |
36 Carry Select Adders | 43 |
361 Optimizing the Block Size to Reduce Delay | 46 |
37 Prefix Addition | 47 |
38 Summary | 52 |
MULTIPLICATION | 55 |
41 Unsigned Binary Multiplication | 56 |
43 CarrySave Array Multipliers CSAM | 60 |
44 Tree Multipliers | 61 |
442 Dadda Tree Multipliers | 65 |
443 Reduced Area RA Multipliers | 68 |
411 Summary | 93 |
DIVISION USING RECURRENCE | 103 |
51 Digit Recurrence | 104 |
52 Quotient Digit Selection | 105 |
521 Containment Condition | 106 |
53 OntheFlyConversion | 108 |
54 Radix 2 Division | 112 |
55 Radix 4 Division with a 2 and Nonredundant Residual | 115 |
551 Redundant Adder | 118 |
56 Radix 4 Division with a 2 and CarrySave Adder | 119 |
57 Radix 16 Division with Two Radix 4 Overlapped Stages | 122 |
58 Summary | 126 |
ELEMENTARY FUNCTIONS | 129 |
61 Generic Table Lookup | 131 |
62 Constant Approximations | 133 |
63 Piecewise Constant Approximation | 134 |
64 Linear Approximations | 136 |
641 Round to Nearest Even | 138 |
65 Bipartite Table Methods | 141 |
651 SBTM and STAM | 142 |
CORDIC | 147 |
67 Summary | 152 |
DIVISION USING MULTIPLICATIVEBASED METHODS | 158 |
72 MultiplicativeDivide Using Convergence | 163 |
73 Summary | 165 |
References | 168 |
| 176 | |
Other editions - View all
Digital Computer Arithmetic Datapath Design Using Verilog Hdl James E. Stine No preview available - 2014 |
Digital Computer Arithmetic Datapath Design Using Verilog HDL James E. Stine No preview available - 2012 |
Common terms and phrases
4-bit by 4-bit 4-bit Unsigned addition b₁ BCLG binary Bitwise bitwise operators block diagram carry-in carry-propagate adder carry-save adder carry3 chapter circuit column Computer Arithmetic constant approximation CORDIC Cout CSAM CSEA Cshiftqm CSKA Dadda Dadda multipliers Dadda Tree dataout datapath datapath design digit recurrence digital system divi2 division divisor elementary functions endmodule equation example fractional bits full adder half adder hardware IEEE implementation input operand instantiation iteration logic memory method module multiplicand multiplication matrix n-bit nand Newton-Raphson number of bits number system one's complement output propagate ptemp1 qi+1 quotient digit selection radix point rca4 reduce registers requires rounding SBTM shifted partial remainder Shifter shown in Figure sign bit signal significant bit state0 stimulus file subtraction sum1 sum2 sum3 table lookup tree multipliers truncated two's complement utilized vectors Verilog Code VLSI Wallace tree zero