Designing with FPGAs and CPLDs

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CRC Press, Jan 9, 2002 - Computers - 224 pages
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* Choose the right programmable logic devices and development tools * Understand the design, verification, and testing issues * Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technolog
  

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Contents

Prehistory Programmable Logic to ASICs
1
11 Programmable Read Only Memories PROMs
2
12 Programmable Logic Arrays PLAs
5
13 Programmable Array Logic PALs
6
14 The Masked Gate Array ASIC
13
15 CPLDs and FPGAs
15
Exercises
16
Complex Programmable Logic Devices CPLDs
17
58 Testing Redundant Logic
113
59 Initializing State Machines
115
510 Observable Nodes
116
512 BuiltIn SelfTest BIST
118
513 Signature Analysis
120
Exercises
123
Verification
131
61 What is Verification?
132

21 CPLD Architectures
18
23 IO Blocks
20
25 Interconnect
21
26 CPLD Technology and Programmable Elements
23
27 Embedded Devices
25
CPLD Selection Criteria
27
Exercises
30
Field Programmable Gate Arrays FPGAs
33
31 FPGA Architectures
34
33 Configurable IO Blocks
37
34 Embedded Devices
40
36 Clock Circuitry
42
37 SRAM vs Antifuse Programming
43
38 Emulating and Prototyping ASICs
45
39 Summary
48
Exercises
51
Universal Design Methodology for Programmable Devices UDMPD
55
41 What is UDM and UDMPD?
56
42 Writing a Specification
57
43 Specification Review
63
46 Verification
65
47 Final Review
68
410 Summary
69
Exercises
70
Design Techniques Rules and Guidelines
73
Objectives
74
52 TopDown Design
88
53 Synchronous Design
92
54 Floating Nodes
108
55 Bus Contention
109
56 OneHot State Encoding
110
57 Design ForTest DFT
111
63 StaticTiming Analysis
136
64 Assertion Languages
137
66 Summary
138
Exercises
139
Electronic Design Automation Tools
141
Objectives
142
72 Testbench Generators
150
73 In Situ Tools
151
75 Automatic Test Pattern Generation ATPG
153
77 BuiltIn SelfTest BIST Generators
154
78 Static Timing Analysis Software
155
79 Formal Verification Software
157
711 Programming Tools
159
712 Summary
160
Exercises
163
Today and the Future
165
82 Special IO Drivers
169
84 ASICs with Embedded FPGA Cells
170
85 Summary
172
Answer Key
173
Chapter 2 Complex Programmable Logic Devices CPLDs
174
Chapter 3 Field Programmable Gate Arrays FPGAs
175
Chapter 4 Universal Design Methodology for Programmable Devices
176
Chapter 5 Design Techniques Rules and Guidelines
178
Chapter 6 Verification
180
Chapter 7 Electronic Design Automation Tools
181
Verilog Code for Schematics in Chapter 5
183
Glossary
205
References
213
About the Author
214
Index
215
Copyright

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About the author (2002)

Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI

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